Digital communication speeds within semiconductor components, between semiconductor components, and between boards and cabinets continue to increase. As speeds increase, testing digital signals does not only involve logic (pattern) testing, but also requires analog parametric testing. With increased speeds, the analog shape of the voltage waveform representing the binary digital data is important. Poor analog parameters such as too long a rise time or too small a voltage swing may result in long term issues that are not uncovered using quick pattern tests. Conversely, analog parameter testing is also useful when debugging failures in logic or pattern tests. Such failures can be caused by systematic phenomena that manifest themselves in waveform shape or timing jitter.
In the present state of the art, separate pieces of equipment are often required to perform logic testing and analog parametric testing, respectively. For example, a logic analyzer or a bit-error-rate tester (BERT) is used for pattern testing and an oscilloscope or jitter analyzer is used for eye diagram testing or jitter testing. As the need to test high-speed digital signals proliferates more into large pin-count devices or circuits, there arises a need to combine some of the capabilities of various pieces of equipment. There is also a need to integrate such capabilities in devices or in small form factors that can fit on application devices or on application boards. For example, a test-related module or component can be placed on a system to perform the digital testing functions. Many high-speed serial receivers now contain a pattern checker for the purpose of digital testing. Adding oscilloscope capability to this basic pattern checking capability is highly desired, but not trivial.
By way of example using commercial test equipment, enabling a BERT or logic analyzer to perform eye diagram analysis simplifies testing and provides enhanced coverage with one piece of equipment instead of two. Such equipment already exists. However, given the contradicting requirements between pattern testing and analog parametric testing, creating such dual-function equipment entails intricate modifications to the basic architecture of the equipment that limits scalability. In particular, to enable a BERT to generate an eye diagram, the former is modified in two main ways. First, analog delay line circuitry is introduced that can delay a data signal or a clock signal, or both, by very small amounts (fraction of data pattern unit interval). The delay line circuitry is area-consuming, bandwidth-limited, and difficult to calibrate. It becomes unmanageable when several test channels are required, as is the case in modern applications or applications in which the pattern tester is integrated within a system.
The other modification that is required involves the front-end capture electronics. Specifically, logic testing merely requires a voltage comparator at the front end of the equipment whereas a measurement such as an eye diagram requires a more complex circuit. To modify a BERT to perform eye diagram measurement, engineers create a window comparator (two or more voltage comparators with similar but slightly offset threshold levels) to detect a transition through a very narrow voltage plane and associated time point. Alternatively, instead of deploying two or more comparators to perform a window comparison, another implementation involves two slightly delayed strobes applied to a single voltage comparator, the delay being a small fraction of the data pattern unit interval. This approach is again complicated and difficult to implement at very high speeds.